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NAPATECH INSIGHTS

APRIL 2018

IN THIS EDITION

Insights from Corvil: Network data analytics & machine learning...
ACLs accelerated...
Reconfigurable computing, stage 2...
Splunk tutorial: quick steps to leverage your solution...
RSA: where the world talks security...
Prepare for the EU General Data Protection Regulation (GDPR)...

INSIGHTS FROM CORVIL
NETWORK DATA ANALYTICS & MACHINE LEARNING

In the electronic trading space, any delay in execution can mean missed opportunities, lost revenue, incompliance and damaged reputation. To avoid this, companies need to measure latency with outstanding accuracy - an activity which demands high-precision timestamping.

In this video, Fergal Toomey, Chief Scientist and Cofounder of Corvil, conveys the value that their customers get from timestamped network data, both for traditional use cases like performance monitoring but also for new use cases such as cybersecurity.

 

WATCH VIDEO

ACLS ACCELERATED

The purpose of Access Control Lists (ACLs) is to provide a basic level of security by restricting traffic to and from a service. But this imposes penalties on the overall performance.

Chief Technology Architect Michael Lilja has explored the performance improvements achievable, if ACLs were accelerated by hardware. See the test results in Lilja's latest blog.

 

READ BLOG

RECONFIGURABLE COMPUTING, STAGE 2

Software programmability is a hot topic across industries. The ability to change the behavior of a system on-the-fly is highly desirable and one of the main drivers behind reconfigurable computing, making it a natural choice both for networking, storage and security.

But when will reconfigurable computing be an option for all – not just FPGA experts? And what should IT orgs do in the interim? Dan Joe Barry, VP Strategy and Market Development, shares his recommendations.

 

READ BLOG

QUICK STEPS TO LEVERAGE YOUR SPLUNK SOLUTION

While Splunk collects a substantial amount of data, it cannot provide the full recording of what has been sent and received on a network. Security and Network Operations Centers therefore need a tool to zoom in on any events that look suspicious.

By integrating Splunk with Napatech Pandion Recorder, all traffic is captured and stored to disk and the data can be quickly retrieved for further investigation and timely remediation. This capability is extremely valuable both for security and compliance purposes, e.g. to meet requirements of the upcoming EU GDPR.

Watch this step-by-step guide to find out how you can leverage your existing Splunk solution by integrating Pandion.

 

WATCH TUTORIAL

 

READ CASE STUDY

RSA: WHERE THE WORLD TALKS SECURITY

Come see us at RSA Conference, one of the world’s leading cybersecurity events, in San Francisco from April 16-20 and experience our reconfigurable computing solutions.

Find us at Booth #2131 in the South Expo where our experts are ready to show you how Napatech’s FPGA-based SmartNICs can reliably accelerate your cybersecurity and open source applications.

 

REIMAGINE YOUR SECURITY

PREPARE FOR GDPR

On 25 May, the General Data Protection Regulation (GDPR) will become fully enforceable throughout the European Union, bringing the most important change in data privacy regulation in 20 years.

At Napatech, it is our business to protect your data. In preparation for GDPR, we have therefore enhanced our subscription management to ensure a persistent high level of relevancy in our communication. 

Please confirm your continued subscription and add your preferences via the link below to avoid missing out on Napatech news, conference information, etc. after 25 May.

 

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Napatech helps companies to reimagine their business, by bringing hyper-scale computing benefits to IT organizations of every size. We enhance open and standard virtualized servers to boost innovation and release valuable computing resources that improve services and increase revenue. Our reconfigurable computing platform™ is based on a broad set of FPGA software for leading IT compute, network and security applications that are supported on a wide array of FPGA hardware designs.

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